Jump to navigationJump to search
The printable version is no longer supported and may have rendering errors. Please update your browser bookmarks and please use the default browser print function instead.

"Although the information we release has been verified and shown to work to the best our knowledge, we cant be held accountable for bricked devices or roots gone wrong."



"CUJO shields your home devices against hacks. CUJO network security firewall protects your computers and IoT devices against malware, ransomware, viruses, and other hacking threats. Think of it as advanced antivirus for all your connected devices - from laptops to smartphones."


Buying devices is expensive and, in a lot of cases our testing leads to bricked equipment. If you would like to help support our group, site, and research please use one of the links below to purchase your next device. Purchase the Cujo at Amazon


The UART Interface runs at ???????? baud at the pinout pictured

Drop to a U-Boot shell by grounding the eMMC data line at the right spot

After stage 1, while stage 2 is booting, hold for 3-4 seconds to ground


Boot Output

OCTEON eMMC stage 1 bootloader (CUJOv1.0)
Loading stage2
Branching to stage 2 at: 0xFFFFFFFF81000000
U-Boot 2013.07 (Development build, svnversion: u-boot:directory, exec:) (Build time: Dec 22 2016 - 21:42:51)
Cavium Inc. OCTEON SDK version 3.1.2, build 568: $Revision: 128476 $
EARLY FILL COUNT                              : 14, cpu_hertz:1000000000, ddr_hertz:666000000
LMC0 Asserting DDR_RESET_L
DDR Reference Hertz = 50000000
clkr:  0, en[5]:  6, clkf:   79, pll_MHz: 4000, ddr_hertz: 666666666, error:  -666666
clkr:  0, en[2]:  3, clkf:   39, pll_MHz: 2000, ddr_hertz: 666666666, error:  -666666
clkr:  1, en[2]:  3, clkf:   79, pll_MHz: 2000, ddr_hertz: 666666666, error:  -666666
clkr:  2, en[2]:  3, clkf:  119, pll_MHz: 2000, ddr_hertz: 666666666, error:  -666666
clkr:  2, en[1]:  2, clkf:   79, pll_MHz: 1333, ddr_hertz: 666666666, error:  -666666
clkr:  0, en[5]:  6, clkf:   79, pll_MHz: 4000, ddr_hertz: 666666666, error:  -666666 <==
LMC0 De-asserting DDR_RESET_L
LMC0: Measured DDR clock: 666666794, cpu clock: 1000000000, ddr clocks: 133333699
LMC0: measured speed: 666666794 hz
Initializing node 0 DDR interface 0, DDR Clock 666666794, DDR Reference Clock 50000000, CPUID 0x000d9602
DDR SPD Table:
DIMM 0: DDR3 UDIMM, non-ECC  D3-56CG107JT9V-999  chksum: 49305 (0xc099) 1.5V
row bits: 15, col bits: 10, bank bits: 3, banks: 8, ranks: 1, dram width: 16, size: 1024 MB